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The limitation of PCI
PCI (Peripheral Component Interconnect) has been the dominant connecting interface for I/O architecture nearly a decade. Its shared bus topology allows the attached PCI devices to arbitrate between themselves to gain the privileged and full data-transferring access (bus) to the south bridge – north bridge - CPU. It’s a simple and cost-effective solution to satisfy the demands from I/O or storage devices when there only a few devices attached.
Nevertheless, with the increase of bandwidth demand from future I/O devices (such as Gigabit Ethernet card, RAID card, and Serial ATA controller), PCI (133MBps - total bandwidth for 32bit, 33MHz) becomes less extensible and its limitation is inevitable. What is more, the more devices are attached; the more noise is injected onto the bus. Certainly the noise will make signal unclear and lower the quality of data transferred on the bus.
Shared Bus Topology of PCI PCI Bandwidth Table
 The most common PCI interface utilized on MB is PCI 32/33 (32bit. 33MHz)
PCI 64bit is released for server board market.
The benefits of PCI Express
PCI Express (as PCIe), originally developed by Intel Corporation, is seen as the latest I/O interface to replace PCI for higher bandwidth. The most obvious improvement of PCI Express is its point-to-point topology, allowing a shared switch to distribute shared resource (bus width) to the attached PCI Express devices according to the priority. In this case, each device has a direct and exclusive access (link) to the switch. Besides, the switch will prioritize the transferred data so real-time applications may get immediate access to the switch.
Point-to-point Topology of PCI Express Link and Lane
 
PCI Express is formerly know as 3GIO. The link of PCIe x1 is composed of 1 lane; the link of PCIe x2 is composed of 2 lanes.
Higher bandwidth is another distinct improvement over PCI. A single lane is capable of transmitting 250MB/s in each direction simultaneously (500MB/s for both directions.) Now PCI Express are available in 5 formats (x1 / x2 / x 3 / x4 / x16) for different bandwidth. PCI Express x2 is composed of 2 lanes and the maximum bandwidth is 500MB/s for single direction and 1000MB/s for both directions.
PCI Express Bandwidth Table
PCI Express x4 / x8 / x12 are not reserved for desk-top market, but server market.
Dual-direction bandwidth will be attainable in the near future.
PCI Express x16 is utilized to replace the current VGA 8X slot interface.
Outlook of PCI Express x1 & x16
PCI Express is still in its infancy and PCI will stumble for a while. Therefore, youmay see PCI Express coexist with PCI on MB for the interim. |
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| Media By AOpen February 01, 2007 |